1. Field of the Invention
This invention generally relates to capacitors, and more particularly, to a wiring structure of laminated capacitors.
2. Background of the Invention
Multilayer printed circuit boards (PCBs) are used in computer systems and electronic devices for interconnecting integrated circuit (IC) chips and other electronic components and devices. In recent years, substantial efforts have been expended in the design of such PCBs and the device arranged thereupon to compensate for voltage fluctuations arising between the power and ground planes in the PCBs. The voltage fluctuations, including switching noises, may be caused by switching or other operations of transistors or other devices in integrated circuits. A common solution to this problem is to place one or more capacitors serving as decoupling capacitors or bypass capacitors coupled between the power and ground planes near the integrated circuits.
Capacitors may be electrically coupled either as discrete elements mounted on the surface of a circuit board, or may be embedded within the circuit boards. Generally, discrete decoupling capacitor or surface mounted device (SMD) decoupling capacitors are often used to reduce undesirable voltage fluctuations. However, SMD decoupling capacitors may become less effective in many modern applications. For example, SMD decoupling capacitors usually occupy a large surface area of a PCB and may limit package design when a smaller board is needed. In addition, since SMD decoupling capacitors are mounted on a PCB, the distance between an IC's power supply and the associated SMD decoupling capacitors are greater than the distance between the IC's power supply and the capacitors embedded within the PCB. Therefore, the use of SMD decoupling capacitors causes greater parasitic inductance and reduces the effectiveness of reduction on voltage fluctuations. In other words, when the operating frequency reaches to hundreds of megaherts (MHz) or even several gigahertz (GHz), SMD decoupling capacitors become ineffective for reducing and stabilizing voltage fluctuations.
FIG. 1 is an impedance curve for exemplary surface mounted capacitors of 1 μF (including low inductance 0612 and 1206 capacitors and a capacitor from Inter-Digitated Capacitors (IDC)) in the frequency range from 0.01 MHz to 1000 MHz. Referring to FIG. 1, the impedance of the capacitors exceeds the desirable impedance (about 0.5 ohm) when the operating frequency reaches hundreds of MHz. The desirable impedance for future designs will be lower, which can be as low as 0.1 ohm or below. Accordingly, none of those SMD capacitors provide a sufficiently low impedance when being operated at high frequencies. Specifically, the poor high frequency performance of surface mounted capacitors make them unsuitable for today's high speed integrated circuits, which may operate at a frequencies in GHz ranges.
Laminated capacitors embedded in a circuit board may save the surface area of circuit boards. In addition, because laminated capacitors may be placed much closer to the integrated circuits, they may minimize parasitic inductance caused by the internal wirings. While the laminated capacitors may provide a better decoupling effect, the laminated capacitors also suffer the parasitic effect due to the inductance from the power and ground vias. The parasitic effect becomes significant as the circuit frequency of the capacitor becomes higher. In the some applications, the capacitor characteristics can be impacted to a stage that the capacitor exhibits significant inductance effects. The threshold frequency for such transition in characteristics is known as the self-resonance frequency. Equation (1) below represents the self-resonance frequency:
                    fr        =                  1                      2            ⁢            π            ⁢                          LC                                                          (        1        )            where fr represents the self-resonance frequency, L represents the parasitic inductance (i.e., equivalent series inductance “ESL”), and C represents the parasitic capacitance (i.e., equivalent series resistance “ESR”). According to Eq. (1) above, the function of a capacitor is lost at a higher frequency than the resonance frequency. In other words, the self-resonance frequency becomes high when the ESL value is small.
In modern high-speed circuit designs, electronic components are required to function well in high frequency regions. Accordingly, it is desirable to lower the ESL and impedance in high frequency circuit applications, thereby increasing its decoupling effect or its bypass bandwidth. Certain wiring structures of a laminated capacitor capable of lowering the value of the parasitic inductance have been developed in recent years.
U.S. Pat. No. 5,161,086 to Howard et al. describes a common wiring connection structure as shown at FIG. 2 for laminated capacitors in a multilayer circuit board. Referring to FIG. 2, the surface mounted integrated circuit 14′ is interconnected with the conductive layers 28′ and 30′ of a laminated capacitor respectively through power and ground leads 34′ and 36′. The power lead 34′ is connected with the conductive layers 28′ and passes through a hole in the conductive layer 30′. Similarly, the ground lead 36′ passes through a hole in the conductive layer 28′ while being electrically coupled with the conductive layer 30′. In this manner, the integrated circuit 14′ is properly connected with both the power and ground planes.
U.S. Pat. No. 6,678,145 to Naito et al. proposes a wiring connection structure of laminated capacitors that may lower the value of the parasitic inductance. FIG. 3(a) is a plan view of the internal structure of the laminated capacitor 41. FIG. 3(b) shows a cross-section along the line III-III shown in FIG. 3(a). Referring to FIG. 3(a), a number of first feedthrough conductors 46 and second feedthrough conductors 47 respectively connect to the first internal electrodes 44 and the second internal electrodes 45. Each of the first feedthrough conductors 46 is arranged adjacent to a second feedthrough conductor 47, thus diversifying the direction of the electric current flowing through the internal electrodes 44 and 45. In this manner, the magnetic fields induced by the electric current flowing through the internal electrodes may be offset and the length of the current flow path may be shorten. As a result, the ESL value may be decreased.